Clocks e DDR
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29-09-2011, 15:10
Mensagem: #2
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RE: Clocks e DDR
Viva,
Sinceramente nunca estudei esse detalhe mas tanto quanto percebi a resposta esta nos links que disponibilizaste Citar:DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte) Citar:DDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus. The two factors combine to require a total of four data transfers per internal clock cycle. With data being transferred 64 bits at a time, DDR2 SDRAM gives a transfer rate of (memory clock rate) × 2 (for bus clock multiplier) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR2 SDRAM gives a maximum transfer rate of 3200 MB/s. Citar:DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte) Na memoria DDR nao tens multiplicador dai a "memoria interna" (aka Memory clock) ser igual a "memoria externa" (aka I/O bus clock). Esse multiplicador deve-se a latencia: Citar:DDR2's bus frequency is boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. The DDR2 prefetch buffer is 4 bits deep, whereas it is two bits deep for DDR and eight bits deep for DDR3. While DDR SDRAM has typical read latencies of between 2 and 3 bus cycles, DDR2 may have read latencies between 4 and 6 cycles. Thus, DDR2 memory must be operated at twice the data rate to achieve the same latency |
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Clocks e DDR - sobrinho - 26-09-2011, 18:55
RE: Clocks e DDR - brunoantunes - 29-09-2011 15:10
RE: Clocks e DDR - sobrinho - 10-10-2011, 19:26
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RE: Clocks e DDR - brunoantunes - 13-10-2011, 14:14
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